Integrated circuit (IC) packages typically include a semiconductor die (e.g., a silicon semiconductor chip) that is suitably protected. Generally, the semiconductor die includes a plurality of electrical contacts (e.g., metal pads or ball grid array (BGA)) for transmitting and receiving signals, supply voltages, electrical, optical and/or other parameters to and from one or more external devices. Typically, the contacts of a semiconductor die are electrically or otherwise coupled respectively to external contacts (e.g., pins or BGA balls) of an IC package. Typically, the external contacts of an IC package have a pitch (i.e., distance between adjacent contacts) larger than the pitch of the contacts of a semiconductor die. Generally then, an IC package employs a complex interconnection (usually referred to as a fan-in/fan-out interconnect) to route the electrical connections from the semiconductor die contacts to the IC package external contacts.
In the past, a fan-in/fan-out interconnect typically consists of several stacked routing layers. Generally, each routing layer includes upper conductive traces disposed on a top surface of the layer, lower conductive traces disposed on a bottom surface of the layer, and a plurality of metalized via holes electrically connecting the upper traces to the lower traces. Usually, the semiconductor die is disposed on the top surface of the upper-most routing layer of the fan-in/fan-out interconnect, and makes electrical contact to its upper conductive traces. Similarly, the external contacts of the IC package are disposed on the bottom surface of the lower-most routing layer of the fan-in/fan-out interconnect, and make electrical contact to its lower conductive traces.
The typical fan-in/fan-out interconnect discussed above has drawbacks that hinder the miniaturization, integration, cost reduction, thermal control, and improved electrical performance of integrated circuits. With regard to miniaturization and integration, the current fan-in/fan-out interconnect generally has limitations on the minimum dimensions and spacing for conductive traces and metalized via holes formed on and through the routing layers of the interconnect. Additionally, the fan-in/fan-out interconnect typically requires a relatively large number of stacked routing layers to provide the necessary fan-in/fan-out interconnection. Furthermore, since the stacked routing layers are mostly made out of a relatively low thermal conductivity dielectric, thermal control of the semiconductor die is generally a challenge.